1. Field of the Invention
The present invention relates to a method for positioning or aligning a mask pattern with a substrate to be exposed in exposure apparatuses used in the manufacture of micro-devices such as semiconductor elements or liquid crystal display elements, for example, and more particularly, it relates to an aligning method particularly applicable when additional patterns are exposed, in a superimposed fashion, on a shot area where plural-layer patterns have already been formed on a substrate to be exposed.
2. Related Background Art
When semiconductor elements or liquid crystal display elements are manufactured by a lithographic technique, exposure apparatuses for exposing a pattern on a photomask or a reticle (hereinafter, "reticle" is explained as an example) onto each of shot areas on a wafer (or glass plate or the like) on which a photosensitive material is coated have been used. Among the exposure apparatuses of this kind, exposure apparatus of so-called step-and-repeat type wherein a wafer stage on which the wafer is mounted is shifted step-by-step (stepping) so that reticle pattern is successively exposed onto each of the shot areas have been widely used. Recently, there have been proposed projection optical apparatuses of so-called step-and-scan type wherein the reticle pattern is exposed in a zone wider than an exposure field of a projection optical system by scanning the reticle and the wafer in synchronous with each other.
For example, since the semiconductor element is formed by superimposing plural-layer circuit patterns on the wafer, for example when second, third and other layer circuit patterns are exposed onto the wafer, positioning (alignment) between each of the shot areas of the wafer on which the circuit patterns have already been formed and an image of the reticle pattern, i.e. alignment between the wafer and the reticle must be effected with high accuracy.
In conventional aligning methods, the above-mentioned alignment was effected by using a last-formed mark layer, i.e. an uppermost mark layer alone as a reference. Thus, positional deviation amounts are gradually accumulated or totalized, thereby causing a problem that the positional deviation amount is increased as the mark layer goes upwardly. More specifically, for example, in the case where it is assumed that wafer marks are formed on all of the mark layers, when a maximum value of an error amount of the alignment of the circuit pattern in an X direction from the wafer mark of the last layer (used as a reference) is .increment.X, in the N-th layer, the positional deviation amount of (N-1).multidot..increment.X will occur at the maximum.
In the semiconductors, patterns related to each other are not necessarily formed on adjacent layers. That is to say, when a pattern formed in an N-th layer film is to be electrically connected to a pattern formed in an (N-2)th layer film, it is necessary to suppress the positional deviation amount between the pattern on the N-th layer and the pattern on the (N-2)th layer as much as possible. However, in the prior art, since the alignment is effected by using the pattern on the last layer as the reference, aligning accuracy between the related layers could not be improved.